(a) Field of the Invention
The present invention relates to a semiconductor memory and a method for manufacturing the same. In particular, it relates to a semiconductor memory such as a DRAM and a method for manufacturing the same.
(b) Description of Related Art
So far, concave capacitive electrodes have been used for DRAMs of a capacitor-under-bitline (CUB) structure having charge storing capacitive elements under bit lines. With use of the concave capacitive electrode in a DRAM, the surface of an interlayer insulating film formed on the DRAM becomes flat. Therefore, the concave capacitive electrode has been paid attention for its usefulness for device miniaturization (e.g., see Japanese Unexamined Patent Publication No. 2002-141424).
Hereinafter, referring to FIGS. 8A and 8B, an explanation is given of a configuration of a conventional embedded semiconductor DRAM including a concave capacitive electrode. FIGS. 8A and 8B are a sectional view and a plan view illustrating a configuration the conventional embedded semiconductor DRAM, respectively. As shown in FIG. 8A, the conventional DRAM includes: a silicon wafer 120; isolation trenches (STIs) 101 formed to surround part of the silicon wafer 120 where a transistor will be formed; a gate insulating film 102a and a gate electrode 102b formed on the silicon wafer 120; a source/drain diffusion layer 103 formed in part of the silicon wafer 120 located at each side of the gate electrode; a first interlayer insulating film 104 formed on the silicon wafer 120, a first bit line contact 105 and a capacitor contact 106 which penetrate the first interlayer insulating film 104 to reach the source/drain diffusion layer 103, respectively; an insulating film 107 formed on the first interlayer insulating film 104; a second interlayer insulating film 108 formed on the insulating film 107; a lower electrode 110 covering the bottom and the sidewalls of a storage node hole 116 which penetrates the second interlayer insulating film 108 to reach the top surface of the capacitor contact 106; a capacitive insulating film 111 covering the lower electrode 110 and the second interlayer insulating film 108 outside the storage node hole 116; an upper electrode 112 covering the capacitive insulating film 111; a third interlayer insulating film 113 formed over the upper electrode 112 to bury the storage node hole 116; a second bit line contact 114 which penetrates the third interlayer insulating film 113 and the second interlayer insulating film 108 to reach the first bit line contact 105; and a first wiring layer 115 formed on the third interlayer insulating film 113 to be connected to the second bit line contact 114.
In the step of manufacturing the semiconductor device shown in FIG. 8A, the upper electrode 112 is subjected to etching using a mask (not shown) formed thereon, thereby forming an opening 117 for forming the second bit line contact 114. The opening 117 is formed above the second interlayer insulating film 108 where the storage node hole 109 is not formed. Then, a contact hole (not shown) is formed to penetrate the third interlayer insulating film 113 and the second interlayer insulating film 108 below the opening 117 and then filled with a conductive film (not shown), thereby forming the second bit line contact 114.
In a plan view of the conventional embedded semiconductor DRAM, as shown in FIG. 8B, a margin c is provided between the storage node hole 116 having a short side length a and a long side length b (planar shape of a capacitor) and the opening 117. The margin c is provided to absorb misalignment of the mask used to form the opening 117.
However, the margin c is narrowed as the device is further miniaturized. Therefore, if the mask for forming the opening 117 is misaligned and etching is carried out with the misaligned mask, the capacitive insulating film 111 and the lower electrode 112 formed in the storage node hole 116 are likely to be etched away. As shown in FIG. 8A, at the top end part H3 of the storage node hole 116 (part of the sidewalls of the hole 116 closer to the top surface of the second interlayer insulating film 108), the upper electrode 112 is removed, whereby the capacitive insulating film 111 and the lower electrode 110 are exposed or partially etched away. As a result, the lower electrode 110 decreases in area, thereby reducing the amount of storable capacitance. Further, the capacitive insulating film which contributes to the capacitance is damaged by the etching to cause leakage current.
In the DRAM which employs the concave capacitive electrode, capacitance cannot be stored in any other parts than the capacitive insulating film formed in the storage node hole 116. Therefore, if the electrode area decreases as a result of the miniaturization, the amount of storable capacitance also decreases. This brings about a problem in that the required amount of capacitance for memory operation cannot be maintained.